
26
MB90640A Series
I
INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER
ASSIGNMENTS TO INTERRUPT SOURCES
: indicates that the interrupt request flag is cleared by the I
2
OS interrupt clear signal (no stop request).
: indicates that the interrupt request flag is cleared by the I
2
OS interrupt clear signal (with stop request).
×
: indicates that the interrupt request flag is not cleared by the I
2
OS interrupt clear signal.
Note: Do not specify I
2
OS activation in interrupt control registers that do not support I
2
OS.
Interrupt source
I
2
OS
support
Interrupt vector
Interrupt control register
Number
Address
ICR
Address
Reset
×
×
×
#08
08
H
FFFFDC
H
—
—
INT 9 instruction
#09
09
H
FFFFD8
H
—
—
Exception
#10
0A
H
FFFFD4
H
—
—
DTP/external interrupt #0
#11
0B
H
FFFFD0
H
ICR00
0000B0
H
DTP/external interrupt #1
#13
0D
H
FFFFC8
H
ICR01
0000B1
H
DTP/external interrupt #2
#15
0F
H
FFFFC0
H
ICR02
0000B2
H
DTP/external interrupt #3
#17
11
H
FFFFB8
H
ICR03
0000B3
H
16-bit reload timer #2
#18
12
H
FFFFB4
H
DTP/external interrupt #4
#19
13
H
FFFFB0
H
ICR04
0000B4
H
16-bit reload timer #3
#20
14
H
FFFFAC
H
DTP/external interrupt #5
#21
15
H
FFFFA8
H
ICR05
0000B5
H
16-bit reload timer #4
#22
16
H
FFFFA4
H
DTP/external interrupt #6
#23
17
H
FFFFA0
H
ICR06
0000B6
H
UART0 send complete
#24
18
H
FFFF9C
H
DTP/external interrupt #7
#25
19
H
FFFF98
H
ICR07
0000B7
H
UART1 send complete
#26
1A
H
FFFF94
H
8/16-bit PPG #0
×
×
#27
1B
H
FFFF90
H
ICR08
0000B8
H
8/16-bit PPG #1
#28
1C
H
FFFF8C
H
16-bit reload timer #0
#29
1D
H
FFFF88
H
ICR09
0000B9
H
16-bit reload timer #1
#30
1E
H
FFFF84
H
Vacancy
#31
1F
H
FFFF80
H
ICR10
0000BA
H
Timebase timer interval interrupt
×
—
#34
22
H
FFFF74
H
ICR11
0000BB
H
Vacancy
#35
23
H
FFFF70
H
ICR12
0000BC
H
UART1 receive complete
#37
25
H
FFFF68
H
ICR13
0000BD
H
UART0 receive complete
#39
27
H
FFFF60
H
ICR14
0000BE
H
Delayed interrupt generation module
×
#42
2A
H
FFFF54
H
ICR15
0000BF
H