
MB90990 Series
2
DS07-13753-3E
■ FEATURES
Clock
Built-in PLL clock frequency multiplication circuit
Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and
multiplication of 1 to 8 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 32 MHz)
Minimum execution time of instruction : 31.25 ns (when operating with 4-MHz oscillation clock and 8-time
multiplied PLL clock)
Clock supervisor (only for devices with J-suffix)
Main clock is monitored
Internal CR oscillation clock (100 kHz typical) can be used as sub clock
16 Mbytes CPU memory space
24-bit internal addressing
Instruction system best suited to controller
Wide choice of data types (bit, byte, word, and long word)
Wide choice of addressing modes (23 types)
Enhanced multiply-divide instructions with sign and RETI instructions
Enhanced high-precision computing with 32-bit accumulator
Instruction system compatible with high-level language (C language) and multitask
Employing system stack pointer
Enhanced various pointer indirect instructions
Barrel shift instructions
Increased processing speed
4-byte instruction queue
Powerful interrupt function
Powerful 8-level, 34-condition interrupt feature
8 channels external interrupts are supported
CPU-independent automatic data transfer function
Expanded intelligent I/O service function (EI2OS) : up to 16 channels
Low power consumption (standby) mode
Sleep mode (a mode that halts CPU operating clock)
Timebase timer mode
Main timer mode (timebase timer mode that is transferred from main clock mode)
PLL timer mode (timebase timer mode that is transferred from PLL clock mode)
Watch mode (a mode that operates sub clock and watch timer only)
Stop mode (a mode that stops oscillation clock and sub clock)
CPU blocking operation mode
Process
CMOS technology
I/O port
General purpose input/output port (CMOS output) :36 ports
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