
MB90960 Series
50
DS07-13749-2E
About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
Use the device with external circuits of the following output impedance for analog inputs:
Recommended output impedance of external circuits are : Approx. 1.5 k
or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period = 0.5
s)
If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
an on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
If the output impedance of an external circuit is too high, the sampling period for the analog voltage may be
insufficient.
If the sampling time cannot be sufficient, connect a capacitor of about 0.1
F to the analog input pin.
To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
(Continued)
R
C
Analog input circuit model
Analog input
During sampling : ON
Comparator
Part number
Analog input
R
C
MB90F962(S),
MB90F967(S)
4.5 V
≤ AVCC ≤ 5.5 V
2.0 k
(Max)
16.0 pF (Max)
4.0 V
≤ AVCC < 4.5 V
8.2 k
(Max)
16.0 pF (Max)
MB90V340E-101/102/103/104
4.5 V
≤ AVCC ≤ 5.5 V
2.0 k
(Max)
14.4 pF (Max)
4.0 V
≤ AVCC < 4.5 V
8.2 k
(Max)
14.4 pF (Max)
Note : The values are reference values.