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參數(shù)資料
| 型號： | MB90F867E |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller CMOS |
| 中文描述： | 16位微控制器專有的CMOS |
| 文件頁數(shù)： | 56/67頁 |
| 文件大?。?/td> | 980K |
| 代理商： | MB90F867E |
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MB90860E Series
56
(13) I
2
C Timing
(T
A
=
–40
°
C to +105
°
C, V
CC
=
5.0 V
±
10
%
, V
SS
=
0.0 V)
Standard-mode
*1 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*3 : The maximum t
HDDAT
have only to be met if the device does not stretch the “L” width (t
LOW
) of the SCL signal.
*4 : A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement
t
SUDAT
≥
250 ns must then be met.
Parameter
Symbol
Condition
Fast-mode*
1
Unit
Min
Max
Min
Max
SCL clock frequency
f
SCL
R
=
1.7 k
,
C
=
50 pF*
2
0
100
0
400
kHz
Hold time (repeated) START condition
SDA
↓
→
SCL
↓
“L” width of the SCL clock
t
HDSTA
4.0
0.6
μ
s
t
LOW
4.7
1.3
μ
s
μ
s
“H” width of the SCL clock
t
HIGH
4.0
0.6
Set-up time for a repeated START condition
SCL
↑
→
SDA
↓
Data hold time
SCL
↓
→
SDA
↓
↑
Data set-up time
SDA
↓
↑
→
SCL
↑
Set-up time for STOP condition
SCL
↑
→
SDA
↑
Bus free time between a STOP and START
condition
t
SUSTA
4.7
0.6
μ
s
t
HDDAT
0
3.45*
3
0
0.9*
4
μ
s
t
SUDAT
250
100
ns
t
SUSTO
4.0
0.6
μ
s
t
BUS
4.7
1.3
μ
s
S
DA
S
CL
t
LOW
t
S
UDAT
t
HD
S
TA
t
BU
S
t
HD
S
TA
t
HDDAT
t
HIGH
t
S
U
S
TA
t
S
U
S
TO
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