![](http://datasheet.mmic.net.cn/330000/MB90F654A_datasheet_16438029/MB90F654A_30.png)
30
MB90650A Series
I
INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO
INTERRUPT SOURCES
: Indicates that the interrupt request flag is cleared by the I
2
OS interrupt clear signal.
: Indicates that the interrupt request flag is cleared by the I
2
OS interrupt clear signal (stop request present).
: Indicates that the interrupt request flag is not cleared by the I
2
OS interrupt clear signal.
Note: For resources in which two interrupt sources share the same interrupt number, the I
2
OS interrupt clear signal
clears both interrupt request flags.
Interrupt source
I
2
OS
support
Interrupt vector
Number
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
Interrupt control register
Number
—
—
—
Address
FFFFDC
H
FFFFD8
H
FFFFD4
H
FFFFD0
H
FFFFCC
H
FFFFC8
H
FFFFC4
H
FFFFC0
H
FFFFBC
H
FFFFB8
H
FFFFB4
H
FFFFB0
H
FFFFAC
H
FFFFA8
H
Address
—
—
—
Reset
INT 9 instruction
Exception
A/D converter
Timebase timer interval interrupt
DTP/external interrupt 0 (External interrupt 0)
×
×
×
ICR00
0000B0
H
×
ICR01
0000B1
H
16-bit free-run timer (I/O timer) overflow
I/O extended serial interface 1
DTP/external interrupt 1 (External interrupt 1)
I/O extended serial interface 2
DTP/external interrupt 2 (External interrupt 2)
ICR02
0000B2
H
ICR03
0000B3
H
DTP/external interrupt 3 (External interrupt 3)
8/16-bit PPG 0 counter borrow
8/16-bit up/down counter/timer 0 compare
8/16-bit up/down counter/timer 0
underflow/overflow, up/down invert
8/16-bit PPG 1 counter borrow
DTP/external interrupt 4/5 (External interrupt 4/5)
ICR04
0000B4
H
ICR05
0000B5
H
#22
FFFFA4
H
#23
#24
#25
#26
#27
#28
#29
FFFFA0
H
FFFF9C
H
FFFF98
H
FFFF94
H
FFFF90
H
FFFF8C
H
FFFF88
H
ICR06
0000B6
H
Output compare (channel 2) match (I/O timer)
ICR07
0000B7
H
Output compare (channel 3) match (I/O timer)
Watch prescaler
DTP/external interrupt 6 (External interrupt 6)
×
ICR08
0000B8
H
8/16-bit up/down counter/timer 1 compare
8/16-bit up/down counter/timer 1
underflow/overflow, up/down invert
Input capture (channel 0) read (I/O timer)
ICR09
0000B9
H
#30
FFFF84
H
#31
#32
#33
#34
#35
#36
#37
#39
#41
#42
FFFF80
H
FFFF7C
H
FFFF78
H
FFFF74
H
FFFF70
H
FFFF6C
H
FFFF68
H
FFFF60
H
FFFF58
H
FFFF54
H
ICR10
0000BA
H
Input capture (channel 1) read (I/O timer)
Output compare (channel 0) match (I/O timer)
ICR11
0000BB
H
Output compare (channel 1) match (I/O timer)
Completion of flash memory write/erase
×
ICR12
0000BC
H
DTP/external interrupt 7 (External interrupt 7)
UART0 transmit complete
I
2
C interface
Delayed interrupt generation module
ICR13
ICR14
0000BD
H
0000BE
H
×
×
ICR15
0000BF
H