參數(shù)資料
型號(hào)： MB90F584CAPMC
元件分類(lèi)： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 88/112頁(yè)
文件大小： 2372K
代理商： MB90F584CAPMC
MB90580C Series
DS07-13710-6E
77
21. Low-Power Consumption Control Circuit
The operation modes of the MB90580C series are the PLL clock, PLL sleep, watch, main clock, main sleep,
stop, and hardware standby modes. The operation modes excluding the PLL clock mode are classified as low-
power consumption modes.
The low power consumption circuit has the following functions.
Main clock mode/Main sleep mode
In either mode, the microcontroller operates only with the main clock (OSC oscillation clock), using the main
clock as the operating clock while suspending the PLL clock (VCO oscillation clock).
PLL sleep mode/Main sleep mode
These modes stop only the operation clock of the CPU, leaving the other clocks active.
Watch mode
The watch mode allows only the time-base timer to operate.
Stop mode/Hardware standby mode
These modes stop oscillation while retaining data at the lowest power consumption. The CPU intermittent
operation function causes the clock supplied to the CPU to operate intermittently when the CPU accesses a
register, internal memory, internal resource, or external bus. This function saves power consumption by de-
creasing the execution speed of the CPU while providing high-speed clock signals to the internal resources.
The PLL clock multiplication factor can be selected from among 1, 2, 3, and 4 using the CS1 and CS0 bits in
the clock selection register.
The WS1 and WS0 bits can be used to set the oscillation settling time for the main clock, which is taken to
wake up from the stop or hardware standby mode.
(1) Register configuration
Low-power consumption mode control register
bit
7
6543210
Address
: 0000A0H
STP SLP
SPL RST TMD CG1 CG0
LPMCR
Access
(W)
(W) (R/W) (W)
(
) (R/W) (R/W) ()
Initial value
(0)
(1)
(0)
(
)
Clock selection register
bit
151413121110
9
8
Address
: 0000A1H
SCM MCM WS1 WS0 SCS MCS CS1 CS0
CKSCR
Access
(R)
(R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(1)
(0)
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