參數(shù)資料
型號： MB90F583CAPMC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 57/112頁
文件大?。?/td> 2372K
代理商： MB90F583CAPMC
MB90580C Series
DS07-13710-6E
49
7.
16-bit I/O timer
The 16-bit I/O timer module consists of one 16-bit free run timer, four input capture circuits, and two output
comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run
timer. Input pulse width and external clock periods can, therefore, be measured.
(1) 16-bit free-run timer (1 channel)
The 16-bit free run timer consists of a 16-bit up-counter, a control register, and a prescaler. The value output
from this timer/counter is used as the base time for the input capture and output compare modules.
Counter operation clock (Selectable from among the following four)
Four internal clock cycles:
φ/4, φ/16, φ/64, φ/256
φ: Machine clock
Interrupts
An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or by compare/match
operation with compare register 0. (The compare/match operation requires the mode setting).
Counter value
An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or when a match with
compare register 0 occurs (The compare/match function can be used by the appropriate mode setting).
Initialization
The counter value can be initialized to “0000H” at a reset, soft clear operation, or a match with compare register
0.
(2) Output compare module (2 channels)
The output compare module consists of two 16-bit compare registers, compare output latches, and control
registers. When the 16-bit free-run timer value matches the compare register value, this module generates an
interrupt while inverting the output level.
Two compare registers can operate independently.
Output pin and interrupt flag for each compare register
A pair of compare registers can be used to control the output pin.
Two compare registers can be used to invert the output pin polarity.
The initial value for each output pin can be set.
An interrupt can be generated by compare/match operation.
(3) Input capture module (4 channels)
The input capture module consists of capture registers and control registers respectively associated with four
independent external input pins. This module can hold the 16-bit free run timer value in the capture register. In
addition, it can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt.
The external input signal edge to be detected can be selected.
One or both of the rising and falling edges can be selected.
Four input capture channels can operate independently.
An interrupt can be generated at a valid edge of the external input signal.
The extended intelligent I/O service can be activated by the interrupt by the input capture module.
相關(guān)PDF資料
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MB90F584CAPMC MICROCONTROLLER, PQFP100
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