參數(shù)資料
型號： MB90F583CAPF
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 56/124頁
文件大?。?/td> 2639K
代理商： MB90F583CAPF
MB90580C Series
56
10. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F
2
MC-16LX
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F
2
MC-16LX CPU to activate the intelligent I/O service or interrupt processing. Two request levels
(“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts
on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.
(1) Register configuration
(2) Block Diagram
Interrupt/DTP enable register
bit
7
6
5
4
3
2
1
0
Address
: 0000030
H
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
ENIR
Access
Initial value
(0)
(0)
(0)
(0)
Interrupt/DTP source register
bit
15
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
14
13
12
11
10
9
8
Address
: 0000031
H
EIRR
Access
Initial value
(X)
(X)
(X)
(X)
Request level setting register (lower)
bit
7
6
5
4
3
2
1
0
Address
: 0000032
H
LB3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
LA3
LB2
LA2
LB1
LA1
LB0
LA0
ELVR lower
Access
Initial value
(0)
(0)
(0)
(0)
Request level setting register (upper)
bit
15
LB7
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
14
LA7
13
LB6
12
LA6
11
LB5
10
LA5
9
8
Address
: 0000033
H
LB4
LA4
ELVR upper
Access
Initial value
(0)
(0)
(0)
(0)
8
8
8
8
8
Interrupt/DTP enable register
Interrupt/DTP source register
Request level setting register
Gate
Source F/F
Edge detect circuit
Request input
F
2
MC-16LX bus
相關PDF資料
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MB90583CAPF 16-bit Proprietary Microcontroller
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