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參數(shù)資料
| 型號： | MB90F574A |
| 廠商： | Fujitsu Limited |
| 英文描述： | Octal Bus Transceivers And Registers With 3-State Outputs 24-CFP -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 9/135頁 |
| 文件大?。?/td> | 2504K |
| 代理商： | MB90F574A |
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9
MB90570 Series
Pin no.
LQFP-120 *
1
QFP-120 *
2
7
Pin name
Circuit type
Function
P37
CLK
E
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the clock (CLK) signal output
pin.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.0 serial data input pin. While UART ch.0 is in
input operation, this input signal is in continuous use, and therefore the
output function should only be used when needed. If shared by output
from other functions, this pin should be output disabled during SIN
operation.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.0 serial data output pin. This function is valid
when UART ch.0 is enabled for data output.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.0 serial clock I/O pin. This function is valid when
UART ch.0 is enabled for clock output.
In single chip mode this is a general-purpose I/O port. It can be set to
open-drain by the ODR4 register.
This is also the UART ch.1 serial data input pin. While UART ch.1 is in
input operation, this input signal is in continuous use, and therefore the
output function should only be used when needed. If shared by output
from other functions, this pin should be output disabled during SIN
operation.
In single chip mode this is a general-purpose I/O port. It can be set to
opendrain by the ODR4 register.
This is also the UART ch.1 serial data output pin. This function is valid
when UART ch.1 is enabled for data output.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
This is also the UART ch.1 serial clock I/O pin. This function is valid when
UART ch.1 is enabled for clock output.
In single chip mode this is a general-purpose I/O port. It can be set to open
drain by the ODR4 register.
These are also the PPG0, 1 output pins. This function is valid when PPG0,
1 output is enabled.
In single chip mode this is a general-purpose I/O port.
9
P40
F
SIN0
10
P41
F
SOT0
11
P42
F
SCK0
12
P43
F
SIN1
13
P44
F
SOT1
14
P45
F
SCK1
15,16
P46,P47
F
PPG0,PPG1
17
P50
SIN2
E
This is also the I/O serial ch.0 data input pin. During serial data input, this
input signal is in continuous use, and therefore the output function should
only be used when needed.
*1: FPT-120P-M05
*2: FPT-120P-M13
,
FPT-120P-M21
(Continued)
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