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參數(shù)資料
| 型號(hào)： | MB90F568 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontrollers |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 45/91頁(yè) |
| 文件大?。?/td> | 484K |
| 代理商： | MB90F568 |
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MB90560/565 Series
45
(2) UART structure
The UART consists of the following 11 blocks:
Clock selector
Receive control circuit
Transmission control circuit
Receive status evaluation circuit
Receive shift register
Transmission shift register
Block diagram
Mode registers (SMR0, SMR1)
Control registers (SCR0, SCR1)
Status registers (SSR0, SSR1)
Input data registers (SIDR0, SIDR1)
Output data registers (SODR0, SODR1)
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
SIDR0/SIDR1
P40/SCK0
<P62/SCK1>
P37/SOT0
<P61/SOT1>
#39 (27
H
)*
<#37 (25
H
)*>
#40 (28
H
)*
<#38 (26
H
)*>
P36/SIN0
<P60/SIN1>
SODR0/SODR1
Control bus
Dedicated baud
rate generator
16-bit reload timer
Pin
Clock
selector
Receive
clock
Receive
control circuit
Start bit
detection circuit
Transmission
start circuit
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Receive
shift register
Receive bit
counter
Pin
Receive
complete
Receive status
evaluation circuit
Internal data bus
Transmit clock
Receive
interrupt signal
Transmit
interrupt signal
Transmission
control circuit
Pin
Transmission
shift register
Transmission start
Receive error detection
signal for EI
2
OS
(to CPU)
SMR0/SMR1
SCR0/SCR1
SSR0/SSR1
* : Interrupt number
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| MB90F583BPMC-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F583CAPFR-GE1 | 制造商:FUJITSU 功能描述: |
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