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MB90560/565 Series
2
(Continued)
Instruction set
Bit, byte, word, and long word data types
23 different addressing modes
Enhanced calculation precision using a 32-bit accumulator
Enhanced signed multiplication and division instructions and RETI instruction
Instruction set designed for high level language (C) and multi-tasking
Uses a system stack pointer
Symmetric instruction set and barrel shift instructions
Program patch function (2 address pointers) .
4-byte instruction queue
Interrupt function
Priority levels are programmable
32 interrupts
Data transfer function
Extended intelligent I/O service function : Up to 16 channels
Low-power consumption modes
Sleep mode (CPU operating clock stops.)
Timebase timer mode (Only oscillation clock and timebase timer continue to operate.)
Stop mode (Oscillation clock stops.)
CPU intermittent operation mode (The CPU operates intermittently at the specified interval.)
Package
LQFP-64P (FTP-64P-M09 : 0.65 mm pin pitch)
QFP-64P (FTP-64P-M06 : 1.00 mm pin pitch)
SH-DIP (DIP-64P-M01 : 1.778 mm pin pitch)
Process : CMOS technology
I
PERIPHERAL FUNCTIONS (RESOURCES)
I/O ports : 51 ports (max.)
Timebase timer : 1 channel
Watchdog timer : 1 channel
16-bit reload timer : 2 channel 5
Multi-function timer
16-bit free-run timer : 1 channel
Output compare : 6 channels
Can output an interrupt request when a match occurs between the count in the 16-bit freerun timer and the
value set in the compare register.
Input capture : 4 channels
On detecting an active edge on the input signal from an external input pin, copies the count value of the 16-
bit freerun timer to the input capture data register and generates an interrupt request.
8/16-bit PPG timer (8-bit
×
6 channels or 16-bit
×
3 channels) The period and duty of the output pulse can
be set by the program.
Waveform generator (8-bit timer : 3 channels)
UART : 2 channels
Full-duplex, double-buffered (8-bit)
Can be set to asynchronous or clock synchronous serial transfer (I/O expansion serial) operation
DTP/external interrupt circuit (8 channels)
External interrupts can activate the extended intelligent I/O service.
Generates interrupts in response to external interrupt inputs.