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參數(shù)資料
| 型號： | MB90F553A |
| 廠商： | Fujitsu Limited |
| 英文描述： | Octal Bus Transceivers And Registers With 3-State Outputs 24-CFP -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 26/58頁 |
| 文件大小： | 695K |
| 代理商： | MB90F553A |
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MB90550A/550B Series
26
(Continued)
Address
Register name
Abbreviated
register name
Read/write
Resource name
Initial value
70
H
Compare register,
channel-0 lower bits
OCCP0
R/W
16-bit
I/O timer
output compare
(ch.0 to ch.3)
XXXXXXXX
71
H
Compare register,
channel-0 upper bits
XXXXXXXX
72
H
Compare register,
channel-1 lower bits
OCCP1
R/W
XXXXXXXX
73
H
Compare register,
channel-1 upper bits
XXXXXXXX
74
H
Compare register,
channel-2 lower bits
OCCP2
R/W
XXXXXXXX
75
H
Compare register,
channel-2 upper bits
XXXXXXXX
76
H
Compare register,
channel-3 lower bits
OCCP3
R/W
XXXXXXXX
77
H
Compare register,
channel-3 upper bits
Compare control status
register, channel-0
Compare control status
register, channel-1
Compare control status
register, channel-2
Compare control status
register, channel-3
XXXXXXXX
78
H
OCS0
R/W
0 0 0 0 _ _ 0 0
79
H
OCS1
R/W
_ _ _ 0 0 0 0 0
7A
H
OCS2
R/W
0 0 0 0 _ _ 0 0
7B
H
OCS3
R/W
_ _ _ 0 0 0 0 0
7C
H
to
9D
H
(Disabled)
9E
H
Program address detection
control register
PACSR
R/W
Address match
detection function
Delayed
interrupt
Low power
consumption control
circuit
0 0 0 0 0 0 0 0
9F
H
Delayed interrupt factor
generation/cancellation register
DIRR
R/W
_ _ _ _ _ _ _ 0
A0
H
Low-power consumption mode
control register
LPMCR
R/W!
0 0 0 1 1 0 0 0
A1
H
Clock select register
CKSCR
R/W!
1 1 1 1 1 1 0 0
A2
H
to
A4
H
(Disabled)
A5
H
Automatic ready function select
register
External address output
control register
Bus control signal select
register
ARSR
W
External bus pin
control circuit
0 0 1 1 _ _ 0 0
A6
H
HACR
W
0 0 0 0 0 0 0 0
A7
H
ECSR
W
0 0 0 0 0 0 0 _
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