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參數(shù)資料
| 型號： | MB90F549GSPFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 34/56頁 |
| 文件大?。?/td> | 757K |
| 代理商： | MB90F549GSPFV |
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MB90540/545 Series
34
*1:The interrupt request flag is cleared by the EI
2
OS interrupt clear signal.
*2:The interrupt request flag is cleared by the EI
2
OS interrupt clear signal. A stop request is available.
N/A:The interrupt request flag is not cleared by the EI
2
OS interrupt clear signal.
Note:
For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags
are cleared by the EI
2
OS interrupt clear signal.
At the end of EI
2
OS, the EI
2
OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI
2
OS and in the meantime another interrupt flag is set by a
hardware event, the later event is lost because the flag is cleared by the EI
2
OS clear signal caused by the
first event. So it is recommended not to use the EI
2
OS for this interrupt number.
If EI
2
OS is enabled, EI
2
OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt sources share the same EI
2
OS Descriptor which
should be unique for each interrupt source. For this reason, when one interrupt source uses the EI
2
OS, the
other interrupt should be disabled.
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