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參數(shù)資料
| 型號： | MB90F523PFF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 29/106頁 |
| 文件大?。?/td> | 1541K |
| 代理商： | MB90F523PFF |
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MB90520 Series
29
(Continued)
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
Descriptions for initial value
0 : The initial value is “0.”
1 : The initial value is “1.”
X : The initial value is indeterminate.
*1: This area is the only external access area having an address of 0000FFH or lower. An access operation to this
area is handled as that to external I/O area.
*2: For details of the “RAM area”, see the memory map.
*3: The “reserved area” is basically disabled because it is used in the system.
*4: “Area used by the system” is the area set by the resistor for evaluating tool.
Notes: For bits initialized by reset operations, the initial value set by the reset operation is listed as an initial value.
Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC, there are cases in which initialization is performed or not performed,
depending on the types of the reset. The value listed is the initial value in cases where initialization is per
formed.
The addresses following 0000FFH are reserved. No external bus access signal is generated.
Boundary ####H between the “RAM area” and the“ reserved area” varies with the product models.
Channels 0 to 3 of the OCU compare register use 16-bit free-run timer 2, while channels 4 to 7 of the OCU
compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (ICU)
0 and 1.
Address
Abbreviated
register
name
Register name
Read/
write
Resource name
Initial value
0000BEH
ICR14
Interrupt control register 14
R/W
Interrupt
controller
00000111 B
0000BFH
ICR15
Interrupt control register 15
R/W
0 0 0 0 0 1 1 1 B
0000C0H
to
0000FFH
(External area)*1
000100H
to
00####H
(RAM area)*2
00####H
to
001FEFH
(Reserved area)*3
001FF0H
PADR0
Program address detection register 0
R/W
Address match
detection
function
XXXXXXXX B
001FF1H
Program address detection register 1
R/W
X X X X X X X X B
001FF2H
Program address detection register 2
R/W
X X X X X X X X B
001FF3H
PADR1
Program address detection register 3
R/W
X X X X X X X X B
001FF4H
Program address detection register 4
R/W
X X X X X X X X B
001FF5H
Program address detection register 5
R/W
X X X X X X X X B
001FF6H
to
001FFFH
(Reserved area)*3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MB90F543GSPFR-GE1 | 制造商:FUJITSU 功能描述: |
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