參數(shù)資料
型號: MB90F523BPMC1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP120
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.40 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù): 60/96頁
文件大?。?/td> 2960K
代理商: MB90F523BPMC1
MB90520B Series
DS07-13707-5E
71
18. Address Match Detection Function
If the program address during program execution matches the value set in one of the detection address setting
registers (PADR) , the address match detection function replaces the instruction being executed with the INT9
instruction and executes the interrupt handler program.
The address match detection function provides a simple method of correcting programming errors (patching)
using RAM or similar.
Address match detection functions
Block diagram
Function
No. of address settings
Two channels (two addresses can be set)
Interrupts
An interrupt is generated when the program address matches the detection
address setting register.
EI2OS support
Not supported by the extended intelligent I/O service (EI2OS) .
ADE1
Reserved Reserved Reserved Reserved
ADD1
ADE0
ADD0
PADR1 (24 bit)
PADR0 (24 bit)
Address latch
PACSR
Internal
data
bus
Detection address setting register
Address detection control register (PACSR)
Comparator
INT9 instruction
(generates an INT9 interrupt)
Reserved : Always set to “0”.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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