參數(shù)資料
型號(hào)： MB90F498GPMC
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LFQFP-64
文件頁(yè)數(shù)： 33/96頁(yè)
文件大?。?/td> 2317K
代理商： MB90F498GPMC
MB90495G Series
DS07-13713-6E
39
4.
16-bit I/O Timer
The 16-bit I/O timer is a complex module comprising one 16-bit free-run timer, and two input capture units (4
input pins) . Clock interval input signals and pulse widths can be measured based on the 16-bit free-run timer.
16-bit I/O Timer Configuration
The 16-bit I/O timer is made up of the following modules :
One 16-bit free-run timer
Two input capture units (each unit having 2 input pins)
16-bit I/O Timer Function
(1) 16-bit free-run timer function
The 16-bit free-run timer consists of a 16-bit up counter, a time counter control status register, and prescaler.
The 16-bit up counter counts up in synchronization with a fraction of the machine clock.
The count clock can be set to one of eight fractions of the machine clock. The external clock signals input to
the 16-bit free-run timer clock input pin (FRCK) can be used as the count clock.
Interrupts can be generated in response to counter value overflows.
Interrupts launch the extended intelligent I/O service (EI2OS) .
The count value of the 16-bit free-run timer can be cleared to “0000H” by either a reset, or software clear via
the timer count clear bit (TCCS : CLR) .
The count value of the 16-bit free-run timer is output to the input capture, and used as the base time for capture
operation.
(2) Input Capture Function
When the input capture detects that an external signal edge has been input to an input pin, it stores the count
value of the 16-bit free-run timer in the input capture data register, for the point at which the edge was detected.
The input capture consists of an input capture register corresponding to four I/O pins, an input capture control
status register, and an edge detection circuit.
When an edge is detected, either rising, falling, or both can be selected.
An interrupt request can be generated to the CPU when an input signal edge is detected.
Interrupts launch the extended intelligent I/O service (EI2OS) .
Since the input capture has four pairs of input pins and input capture data registers, it can measure up to 4
phenomena.
Block Diagram of 16-bit I/O Timer
Internal data bus
Input capture
Dedicated
bus
16-bit
free-run timer
16-bit free-run timer: The counter value of the 16-bit free-run timer is used as the base time of the input capture.
Input capture: Input capture detects rising, falling and both edges for external signals input to input pins, and stores
the counter value of the 16-bit free-run timer. Interrupts can be generated in response to input signal
edge detection.
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