參數(shù)資料
型號: MB90F488BPMC
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 104/124頁
文件大?。?/td> 3283K
代理商: MB90F488BPMC
MB90480B/485B Series
80
DS07-13722-11E
22.
μDMAC
The
μDMAC is a simplified DMA module with functions equivalent to EI2OS. The μDMAC has 16 DMA data
transfer channels, and provides the following functions.
Automatic data transfer between peripheral resources (I/O) and memory.
CPU program execution stops during DMA operation.
Incremental addressing for transfer source and destination can be turned on/off.
DMA transfer control from the
μDMAC enable register, μDMAC stop status register, μDMAC status register,
and descriptor.
Stop requests from resources can stop DMA transfer.
When DMA transfer is completed, the
μDMAC status register sets a flag in the bit for the corresponding channel
on which transfer was completed, and outputs a completion interrupt to the interrupt controller.
(1) Register List
μDMAC enable register
Initial value
DERH : 0000ADH
00000000B
μDMAC enable register
Initial value
DERL : 0000ACH
00000000B
μDMAC stop status register
Initial value
DSSR : 0000A4H
00000000B
μDMAC status register
Initial value
DSRH : 00009DH
00000000B
μDMAC status register
Initial value
DSRL : 00009CH
00000000B
R/W
15
14
13
12
11
10
9
8
EN14
EN15
EN13
EN12
EN11
EN10
EN9
EN8
R/W
76
5
4
3
2
1
0
EN6
EN7
EN5
EN4
EN3
EN2
EN1
EN0
R/W
76
5
4
3
2
1
0
STP6
STP7
STP5
STP4
STP3
STP2
STP1
STP0
R/W
15
14
13
12
11
10
9
8
DE14
DE15
DE13
DE12
DE11
DE10
DE9
DE8
R/W
76
5
4
3
2
1
0
DE6
DE7
DE5
DE4
DE3
DE2
DE1
DE0
R/W
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