參數(shù)資料
型號(hào): MB90F488B
廠商: Fujitsu Limited
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16位微控制器專有
文件頁數(shù): 80/120頁
文件大?。?/td> 1241K
代理商: MB90F488B
MB90480/485 Series
80
22.
μ
DMAC
The
μ
DMAC is a simplified DMA module with functions equivalent to EI
2
OS. The
μ
DMAC has 16 DMA data
transfer channels, and provides the following functions.
Automatic data transfer between peripheral resources (I/O) and memory.
CPU program execution stops during DMA operation.
Incremental addressing for transfer source and destination can be turned on/off.
DMA transfer control from the
μ
DMAC enable register,
μ
DMAC stop status register,
μ
DMAC status register,
and descriptor.
Stop requests from resources can stop DMA transfer.
When DMA transfer is completed, the
μ
DMAC status register sets a flag in the bit for the corresponding channel
on which transfer was completed, and outputs a completion interrupt to the interrupt controller.
(1) Register List
μ
DMAC enable register
Initial value
00000000
B
DERH : 0000AD
H
μ
DMAC enable register
Initial value
00000000
B
DERL : 0000AC
H
μ
DMAC stop status register
Initial value
00000000
B
DSSR : 0000A4
H
μ
DMAC status register
Initial value
00000000
B
DSRH : 00009D
H
μ
DMAC status register
Initial value
00000000
B
DSRL : 00009C
H
R/W
R/W
15
14
13
12
11
10
9
8
EN14
EN15
EN13
EN12
EN11
EN10
EN9
EN8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
EN6
EN7
EN5
EN4
EN3
EN2
EN1
EN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
STP6
STP7
STP5
STP4
STP3
STP2
STP1
STP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
DE14
DE15
DE13
DE12
DE11
DE10
DE9
DE8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
DE6
DE7
DE5
DE4
DE3
DE2
DE1
DE0
R/W
R/W
R/W
R/W
R/W
R/W
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