參數(shù)資料
型號: MB90F482PFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 46/120頁
文件大?。?/td> 1241K
代理商: MB90F482PFV
MB90480/485 Series
46
6.
8/16-bit up/down Counter/Timer
8/16-bit up/down counter/timer consists of up/down counter/timer circuits including six event input pins, two
8-bit up/down counters, two 8-bit reload/compare registers, as well as the related control circuits.
(1) Principal Functions
8-bit count register enables counting in the range 0 to 256.
(In 16-bit
×
1 mode, counting is enabled in the range 0 to 65535)
Count clock selection provides four count modes.
Count modes
Timer mode
In timer mode, there is a choice of two internal count clock signals.
Count clock
125 ns (8 MHz :
×
2)
In up/down count mode, there is a choice of trigger edge detection for the input signal from external pins.
Edge detection
Falling edge detection
In phase differential count mode, to handle encoder counting for motors, the encoder A-phase, B-phase, and
Z-phase are each input, enabling easy and highly accurate counting of angle of rotation, speed of rotation, etc.
The ZIN pin provides a selection of two functions.
ZIN pin
Counter clear function
A compare function and reload function are provided, each for use separately or in combination. Both functions
can be activated together for up/down counting in any desired bandwidth.
Compare/reload function
Compare function (output interrupt at compare events)
Compare function (output interrupt and clear counter at compare
events)
Reload function (output interrupt and reload at underflow events)
Individual control over interrupts at compare, reload (underflow) and overflow events.
Count direction flag enables identification of the last previous count direction.
Interrupt generated when count direction changes.
Up/down count mode
Phase differential down count mode (
×
2)
Phase differential down count mode (
×
8)
(at 16 MHz operation)
0.5
μ
s (2 MHz :
×
8)
Rising edge detection
Both rising/falling edge detection
Edge detection disabled
Gate functions
Compare/reload function
(output interrupt and clear counter at compare events, output interrupt
and reload at underflow events)
Compare/reload disabled
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