參數(shù)資料
型號: MB90F482
廠商: Fujitsu Limited
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16位微控制器專有
文件頁數(shù): 32/120頁
文件大?。?/td> 1241K
代理商: MB90F482
MB90480/485 Series
32
(Continued)
×
: Interrupt request flag is not cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal (stop request present) .
*1 : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time.
*2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE
=
1) to disable
(TMCSR : INTE
=
0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to 0 : 111
B
) , then set
the INTE bit to 0.
Note : If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request
flags at the EI
2
OS/
μ
DMAC interrupt clear signal. Therefore if either of the two sources uses the EI
2
OS/
μ
DMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corre-
sponding resource should be set to “0” and interrupt requests from that resource should be handled by
software polling.
Interrupt source
Clear of
EI
2
OS
μ
DMAC
channel
number
Interrupt vector
Interrupt control register
Number
Address
Number
Address
I
2
C interface
(MB90485 series only)
×
×
#39
FFFF60
H
ICR14
0000BE
H
A/D conversion
15
#40
FFFF5C
H
Flash write/erase,
timebase timer, watch timer *
1
×
×
#41
FFFF58
H
ICR15
0000BF
H
Delay interrupt generator
module
×
×
#42
FFFF54
H
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