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參數(shù)資料
| 型號(hào)： | MB90F457S |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 41/78頁(yè) |
| 文件大?。?/td> | 680K |
| 代理商： | MB90F457S |
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MB90455 Series
41
8/16-bit PPG timer0 block diagram
PPG0
CLK
R
S
Q
PEN0
PE0
PIE0 PUF0
PCS2
PPG0/1 count clock selection register (PPG01)
PCS0 PCM2 PCM1 PCM0
PCS1
3
2
Re-
served
Re-
versed
“H” level side data bus
“L” level side data bus
PPG0 operation mode control
register (PPGC0)
PPG0 reload
register
Interrupt
request output*
Operation mode
control signal
Select
signal
Reload register
L/H selector
PPLH0
(“H” level side)
PPLL0
(“L” level side)
PPG0 temporary
buffer 0(PRLBH0)
Count start
value
Reload
Clear
PPG0 down counter
(PCNT0)
Underflow
PPG1 underflow
PPG0 underflow
(To PPG1)
Pulse selector
PPG0
output latch
PPG output control circuit
Pin
Time-base timer output
(512/HCLK)
Peripheral clock (1/
φ
)
Peripheral clock (2/
φ
)
Peripheral clock (4/
φ
)
Peripheral clock (8/
φ
)
Peripheral clock (16/
φ
)
Count clock
selector
Select signal
Reserved : Reserved bit
HCLK
: Oscillation clock frequency
φ
: Machine clock frequency
*
: Interrupt output of 8/16-bit PPG timer 0 is incorporated into one by the OR circuit against
interrupt output of 8/16-bit PPG timer 1.
: Undefined
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