• 參數(shù)資料
    型號： MB90F444G
    廠商： Fujitsu Limited
    英文描述： 16-bit Proprietary Microcontroller
    中文描述： 16位微控制器專有
    文件頁數(shù)： 8/61頁
    文件大?。?/td> 644K
    代理商： MB90F444G
    MB90440G Series
    8
    (Continued)
    Pin No.
    Pin name
    Circuit type
    Function
    14
    P34
    H
    General I/O port with programmable pullup. This function is enabled
    in the single-chip mode or when hold function is disabled.
    HRQ
    Hold request input pin. This function is enabled when the external
    bus is in enable mode and the hold function is enabled.
    15
    P35
    H
    General I/O port with programmable pullup. This function is enabled
    in the single-chip mode or when hold function is disabled.
    HAK
    Hold acknowledge output pin. This function is enabled when the ex-
    ternal bus is in enable mode and the hold function is enabled.
    16
    P36
    H
    General I/O port with programmable pullup. This function is enabled
    in the single-chip mode or when the external ready function is dis-
    abled.
    RDY
    Ready input pin. This function is enabled when the external bus is
    in enable mode and the external ready function is enabled.
    17
    P37
    H
    General I/O port with programmable pullup. This function is enabled
    in the single-chip mode or when CLK output is disabled.
    CLK
    CLK output pin. This function is enabled when the external bus is in
    enable mode and CLK output is enabled.
    18
    P40
    G
    General I/O port. This function is enabled when serial data output
    of UART0 is disabled.
    SOT0
    Serial data output pin for UART0. This function is enabled when
    UART0 enables serial data output.
    19
    P41
    G
    General I/O port. This function is enabled when clock output of
    UART0 is disabled.
    SCK0
    Serial clock I/O pin for UART0. This function is enabled when
    UART0 enables serial clock output.
    20
    P42
    G
    General I/O port. This function is always enabled.
    SIN0
    Serial data input pin for UART0. Set the corresponding DDR regis-
    ter to input if this function is used.
    21
    P43
    G
    General I/O port. This function is always enabled.
    SIN1
    Serial data input pin for UART1. Set the corresponding DDR regis-
    ter to input if this function is used.
    22
    P44
    G
    General I/O port. This function is enabled when serial clock output
    of UART1 is disabled.
    SCK1
    Serial clock I/O pin for UART1. This function is enabled when
    UART1 enables serial clock output.
    24
    P45
    G
    General I/O port. This function is enabled when serial data output
    of UART1 is disabled.
    SOT1
    Serial data output pin for UART1. This function is enabled when
    UART1 enables serial data output.
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