參數(shù)資料
型號： MB90F443GPF
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 10/61頁
文件大小： 644K
代理商： MB90F443GPF
MB90440G Series
10
(Continued)
Pin No.
Pin name
Circuit type
Function
59 to 60
P76 to P77
D
General I/O ports. This function is enabled when the OCU disables
output.
OUT2 to OUT3
Event output pins for output compares OCU2 and OCU3. This
function is enabled when the OCU enables output.
IN6 to IN7
Trigger input pins for input captures ICU6 and ICU7. Set the corre-
sponiding DDR register to input and prohibit the OCU output if this
function is used.
61 to 64
P80 to P83
D
General I/O ports. This function is enabled when 8/16-bit PPG timer
disables waveform output.
PPG0 to PPG3
Output pins for 8/16-bit PPG timer. This function is enabled when
8/16-bit PPG timer enables waveform output.
65 to 66
P84 to P85
D
General I/O ports. This function is enabled when the OCU disables
output.
OUT0 to OUT1
Event output pins for output compares OCU0 and OCU1. This func-
tion is enabled when the OCU enables output.
67
P86
D
General I/O port. This function is always enabled.
TIN1
Input pin for the 16-bit reload timers 1. Set the corresponding DDR
register to input if this function is used.
68
P87
D
General I/O port. This function is enabled when the 16-bit reload
timers 0 disables output.
TOT1
Output pin for the 16-bit reload timers 1. This function is enabled
when the reload timers 1 enables output.
69 to 70
P90 to P91
D
General I/O ports. This function is always enabled.
INT0 to INT1
External interrupt request input pins for INT0 to INT3. Set the cor-
responding DDR register to input if this function is used.
71
P92
D
General I/O port. This function is enabled when CAN2 disables out-
put.
TX2
TX output pin for CAN2. This function is enabled when CAN2 en-
ables output.
72
P93
D
General I/O port. This function is always enabled.
RX2
RX input pin for CAN2 interface. When the CAN function is used,
output from the other functions must be stopped.
73
P94
D
General I/O port. This function is enabled when CAN0 disables out-
put.
TX0
TX output pin for CAN0. This function is enabled when CAN0 en-
ables output.
74
P95
D
General I/O port. This function is always enabled.
INT2
External interrupt request input pin for INT2. Set the corresponding
DDR register to input if this function is used.
RX0
RX input pin for CAN0 interface. When the CAN function is used,
output from the other functions must be stopped.
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