
MB90435 Series
43
 (8) Hold Timing
 (MB90F438L (S) /437L (S) /438L (S)  : V
CC
=
 3.5 V to 5.5 V, V
SS
=
 AV
SS
=
 0.0 V, T
A
=
40 
°
C to 
+
105 
°
C)
 (MB90F439 (S) /439 (S) /V540G : V
CC
=
 5.0 V 
±
 10
%
, V
SS
=
 AV
SS
=
 0.0 V, T
A
=
40 
°
C to 
+
105 
°
C)
Note : There is more than 1 cycle from the time HRQ is read to the time the HAK is changed.
 (9) UART0/1, Serial I/O Timing
 (MB90F438L (S) /437L (S) /438L (S)  : V
CC
=
 3.5 V to 5.5 V, V
SS
=
 AV
SS
=
 0.0 V, T
A
=
40 
°
C to 
+
105 
°
C)
 (MB90F439 (S) /439 (S) /V540G : V
CC
=
 5.0 V 
±
 10
%
, V
SS
=
 AV
SS
=
 0.0 V, T
A
=
40 
°
C to 
+
105 
°
C)
Notes : 
 AC characteristic in CLK synchronized mode.
 C
L
 is load capacity value of pins when testing.
 For t
CP
 (Machine clock cycle time) , refer to “ (1) Clock Timing”.
Parameter
Symbol
Pin name
Condition
Value
Units
Remarks
Min
Max
Pin floating
→
HAK
↓
time
HAK
↑
time
→
Pin valid time
t
XHAL
HAK
30
t
CP
ns
t
HAHV
HAK
t
CP
2 t
CP
ns
Parameter
Symbol
Pin name
Condition
Value
Units Remarks
Min
Max
Serial clock cycle time
t
SCYC
SCK0 to SCK2
Internal clock opera-
tion output pins are 
C
L
=
 80 pF 
+
 1 TTL.
8 t
CP
ns
SCK
↓→
SOT delay time
t
SLOV
SCK0 to SCK2, 
SOT0 to SOT2
80
80
ns
Valid SIN
→
SCK
↑
t
IVSH
SCK0 to SCK2, 
SIN0 to SIN2
100
ns
SCK
↑→
Valid SIN hold time
t
SHIX
SCK0 to SCK2, 
SIN0 to SIN2
60
ns
Serial clock “H” pulse width
t
SHSL
SCK0 to SCK2
External clock oper-
ation output pins are 
C
L
=
 80 pF 
+
 1 TTL.
4 t
CP
ns
Serial clock “L” pulse width
t
SLSH
SCK0 to SCK2
4 t
CP
ns
SCK
↓→
SOT delay time
t
SLOV
SCK0 to SCK2, 
SOT0 to SOT2
150
ns
Valid SIN
→
SCK
↑
t
IVSH
SCK0 to SCK2, 
SIN0 to SIN2
60
ns
SCK
↑→
Valid SIN hold time
t
SHIX
SCK0 to SCK2, 
SIN0 to SIN2
60
ns
HAK
t
XHAL
t
HAHV
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
Each pin
High impedance
 Hold Timing