參數(shù)資料
型號(hào)： MB90F395HPMT
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120
封裝： PLASTIC, LQFP-120
文件頁數(shù)： 52/74頁
文件大小： 886K
代理商： MB90F395HPMT
MB90390 Series
56
(5) UART2/3 (LIN/SCI)
Bit setting : ESCR2/3 : SCES
= 0, ECCR2/3 : SCDE = 0
(TA
= 40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Notes :
CL is load capacity value of pins when testing.
Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB90390 series hardware manual”.
tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
Parameter
Symbol
Pin
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK2/3
Internal clock
operation output pins
are
CL
= 80 pF + 1 TTL.
5 tCP
ns
SCK
↓ → SOT delay time
tSLOVI
SCK2/3, SOT2/3
50
+50
ns
Valid SIN
→ SCK ↑
tIVSHI
SCK2/3, SIN2/3
tCP + 80
ns
SCK
↑ → Valid SIN hold time
tSHIXI
SCK2/3, SIN2/3
0
ns
Serial clock “L” pulse width
tSLSH
SCK2/3
External clock
operation output pins
are
CL
= 80 pF + 1 TTL.
3 tCP
tR
ns
Serial clock “H” pulse width
tSHSL
SCK2/3
tCP + 10
ns
SCK
↓ → SOT delay time
tSLOVE
SCK2/3, SOT2/3
2 tCP + 60
ns
Valid SIN
→ SCK ↑
tIVSHE
SCK2/3, SIN2/3
30
ns
SCK
↑ → Valid SIN hold time
tSHIXE
SCK2/3, SIN2/3
tCP + 30
ns
SCK fall time
tF
SCK2/3
10
ns
SCK rise time
tR
SCK2/3
10
ns
SCK
SOT
SIN
tSCYC
tIVSHI
tSHIXI
0.8 V
2.4 V
0.8 V
VIH
VIL
tSLOVI
VIH
VIL
Internal Shift Clock Mode
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