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MB90350E Series
24
■
HANDLING DEVICES
1.
Preventing latch-up
CMOS IC chips may suffer latch
-
up under the following conditions
:
A voltage higher than V
CC
or lower than V
SS
is applied to an input or output pin.
A voltage higher than the rated voltage is applied between V
CC
SS
pins.
The AV
CC
power supply is applied before the V
CC
voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AV
CC
, AVRH) exceed the digital
power-supply voltage (V
CC
) .
Treatment of unused pins
2.
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 k
.
Unused I/O pins should be set to the output state and can be left open, or the input state with the above described
connection.
Using external clock
3.
To use external clock, drive the X0 pin and leave X1 pin open.
4.
Precautions for when not using a sub clock signal
X0A and X1A are oscillation pins for sub clock. If you do not connect pins X0A and X1A to an oscillator, use
pull-down handling on the X0A pin, and leave the X1A pin open.
Notes on during operation of PLL clock mode
5.
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
X0
X1
MB90350E Series
Open