參數(shù)資料
型號： MB90F342CEPMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 70/92頁
文件大小： 2532K
代理商： MB90F342CEPMC
MB90340E Series
72
DS07-13747-4E
(13) I2C Timing
(TA
= –40°C to +105°C, VCC = 5.0 V ± 10%, VSS = 0.0 V)
*1: For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2: R,C: Pull-up resistor and load capacitor of the SCL and SDA lines.
*3: The maximum tHDDAT meets the requirement that it does not extend the “L” width (tLOW) of the SCL signal.
*4: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT
≥ 250 ns must then be met.
Parameter
Symbol
Condition
Standard-mode
Fast-mode*1
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1.7 kΩ,
C
= 50 pF*2
0
100
0
400
kHz
Hold time (repeated) START condition
SDA
↓ → SCL ↓
tHDSTA
4.0
0.6
μs
“L” width of the SCL clock
tLOW
4.7
1.3
μs
“H” width of the SCL clock
tHIGH
4.0
0.6
μs
Set-up time (repeated) START condition
SCL
↑ → SDA ↓
tSUSTA
4.7
0.6
μs
Data hold time
SCL
↓ → SDA ↓ ↑
tHDDAT
0
3.45*3
00.9*4
μs
Data set-up time
SDA
↓ ↑ → SCL ↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL
↑ → SDA ↑
tSUSTO
4.0
0.6
μs
Bus free time between a STOP and START
condition
tBUS
4.7
1.3
μs
SDA
SCL
tLOW
tSUDAT
tHDSTA
tBUS
tHDSTA
VIL
VIH
VIL
VIH
VIL VIL
VIL
VIH
tHDDAT
tHIGH
tSUSTA
tSUSTO
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