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參數(shù)資料
| 型號(hào)： | MB90947A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 55/68頁(yè) |
| 文件大小： | 331K |
| 代理商： | MB90947A |
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MB90945 Series
55
(8) I
2
C Timing
(T
A
=
40
°
C to
+
105
°
C, V
CC
=
3.5V to 5.5V, V
SS
=
AV
SS
=
0.0 V)
Standard-mode
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum t
HDDAT
only has to be met if the devie does not stretch the “L” width (t
LOW
) of the SCL signal.
*3 : A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement
t
SUDAT
≥
250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
Parameter
Symbol Condition
Fast-mode
*4
Unit
Min
Max
Min
Max
SCL clock frequency
f
SCL
R
=
1.3 k
,
C
=
50 pF*
1
0
100
0
400
kHz
Hold time (repeated) START condition
SDA
↓ →
SCL
↓
“L” width of SCL clock
t
HDSTA
4.0
0.6
μ
s
t
LOW
4.7
1.3
μ
s
μ
s
“H” width of SCL clock
t
HIGH
4.0
0.6
Set-up time for a repeated START condition
SCL
↑ →
SDA
↓
Data hold time
SCL
↑ →
SDA
↓↑
Data set-up time
SDA
↓↑ →
SCL
↑
Set-up time for STOP condition
SCL
↑ →
SDA
↑
Bus free time between STOP and START
condition
t
SUSTA
4.7
0.6
μ
s
t
HDDAT
0
3.45*
2
0
0.9*
3
μ
s
t
SUDAT
250
100
ns
t
SUSTO
4.0
0.6
μ
s
t
BUS
4.7
1.3
μ
s
SDA
SCL
t
LOW
t
HIGH
t
HDDAT
t
HDSTA
t
SUDAT
t
SUSTA
t
HDSTA
t
SUSTO
t
BUS
I
2
C Timing
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