參數(shù)資料
型號(hào): MB90676PF
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-Bit Proprietary Microcontroller
中文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 66/106頁
文件大?。?/td> 1648K
代理商: MB90676PF
MB90670/675 Series
66
12. DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral)/external interrupt circuit is located between peripheral equipment connected
externally and the F
2
MC-16L CPU and transmits interrupt requests or data transfer requests generated by
peripheral equipment to the CPU, generates external interrupt request and starts the extended intelligent I/O
service (EI
2
OS).
(1) Register Configuration
DTP/interrupt factor register (EIRR)
Address
000029
H
bit 7 . . . . . . . . . . . .
ER3
ER2
ER1
ER0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
(ENIR)
Initial value
- - - - 0000
B
R/W
R/W
R/W
R/W
Address
000028
H
bit 15 . . . . . . . . . . . .
EN3
EN2
EN1
EN0
(EIRR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
Initial value
- - - - 0000
B
Address
00002A
H
bit 15 . . . . . . . . . . . .
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
(Vacancy)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000
B
DTP/interrupt enable register (ENIR)
Request level setting register (ELVR)
R/W : Readable and writable
— : Unused
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