2.12 Low Power Consumption Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization Wait
Time, Clock Multiplier Function)
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Chapter 2: Hardware
[Bit 10] MCS
This bit selects either the main clock or PLL clock as the machine clock. Write ‘0’ to this bit to
select the PLL clock, or write ‘1’ to select the main clock. If the value ‘1’ is overwritten by ‘0,’ the
PLL clock oscillation stabilization wait period is generated, and therefore the timebase timer will be
automatically cleared, and the TBOF bit in the timebase timer control register will also be cleared.
Note that the length of the PLL clock oscillation stabilization wait period is fixed at 213 main clock
cycles (approximately 2 ms at source oscillation of 4 MHz).
Note also that when the main clock is selected as the operating clock, the operating clock frequency
will be the main clock divided by 2 (at source oscillation of 4 MHz, the operating clock speed will
be 2 MHz).
This bit is initialized to ‘1’ by power-on or watchdog reset.
[CAUTION]
When overwriting the MCS bit value ‘1’ with the value ‘0,’ always be sure that the TBIE
bit or the CPU's ILM bit is used to mask the timebase timer interrupt.
[Bits 9, 8] CS1, CS0
These bits determine the PLL clock multiplier rate. These bits cannot be reset from external pins or
by the RST bit, but are initialized to ‘00’ by a power-on reset.
When the MCS bit is ‘0,’ write access to these bits is prohibited. Be sure to set the MCS bit
temporarily to ‘1’ (main clock mode) before rewriting the CS bits.
These bits are read/write-enabled.
Table 2.12.3 CS Bit Settings
[CAUTION]
At 5 V operating voltage, the oscillator has a range of 3 MHz to 16 MHz. However,
proper operation cannot be obtained when using any multiplier that yields a frequency
exceeding the maximum operating frequency of the MB90660A CPU and peripheral
resources, which is 16 MHz. Thus, for example, if the source oscillation is 16 MHz, 1x is
the only permissible multiplier.
Also, the lowest operating frequency of the VCO oscillator is 4 MHz, so that no frequency
lower than this level may be selected.
CS1
CS0
Machine clock (at source oscillation of 4 MHz)
0
4 MHz (operating frequency = oscillator frequency)
0
1
8 MHz (operating frequency = oscillator frequency × 2)
1
0
12 MHz (operating frequency = oscillator frequency × 3)
1
16 MHz (operating frequency = oscillator frequency × 4)