參數資料
型號: MB90652A
廠商: Fujitsu Limited
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16位微控制器專有
文件頁數: 69/120頁
文件大?。?/td> 1690K
代理商: MB90652A
69
MB90650A Series
15. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F
2
MC-16L CPU can be generated and cleared by software using this module.
(1) Register Details
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,
considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for
register access.
(2) Block Diagram
Address : 00009F
H
R0
R/W
Initial value
-------0
B
Delayed interrupt generation /release register (DIRR)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
: Readable and writable
: Unused
Delayed interrupt generation/release decoder
Interrupt latch
I
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相關代理商/技術參數
參數描述
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MB90653APFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller