參數(shù)資料
型號: MB90632A
廠商: Fujitsu Limited
英文描述: 16-Bit Proprietary Microcontroller(16位專用微控制器)
中文描述: 16位微控制器專利(16位專用微控制器)
文件頁數(shù): 64/107頁
文件大小: 999K
代理商: MB90632A
64
MB90630A Series
15. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F
2
MC-16L CPU can be generated and cleared by software using this module.
(1) Register Configuration
(2) Register Details
Delayed interrupt request register (DIRR)
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,
considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for
register access.
(3) Block Diagram
00009F
H
15
14
13
12
11
10
9
R0
8
Address:
bit
Delayed interrupt request register
(DIRR)
00009F
H
15
14
13
12
11
10
9
R0
8
Address:
bit
Initial value
-------0
B
(R/W)
Delayed interrupt generate/clear decoder
Interrupt latch
F
2
M
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