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MB90610A Series
2. UART 0/1/2 (SCI)
UART 0/1/2 are serial I/O ports that can be used for CLK asynchronous (start-stop synchronization) or CLK
synchronous (I/O expansion serial) data transfer. The ports have the following features.
Full duplex, double buffered
Supports CLK asynchronous (start-stop synchronization) and CLK synchronous (I/O expansion serial) data
transfer
Multi-processor mode support
Built-in dedicated baud rate generator
CLK asynchronous: 62500/31250/19230/9615/4808/2404/1202 bps
CLK synchronous: 2 M/1 M/500 K/250 K bps
Supports flexible baud rate setting using an external clock
Error detect function (parity, framing, and overrun)
NRZ type transmission signal
Intelligent I/O service support
(1) Register Configuration
bit
Read/write
Initial value
bit
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SCR
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(1)
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
10
9
8
MD1
MD0
CS2
CS1
CS0
–
SCKE SOE
SMR
(R/W)
(0)
(R/W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(–)
(–)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
Read/write
Initial value
Serial control register
Address: channel 0 000021
H
: channel 1 000025
H
: channel 2 000045
H
Serial mode register
Address: channel 0 000020
H
: channel 1 000024
H
: channel 2 000044
H
bit
Read/write
Initial value
bit
PE
ORE
FRE RDRF TDRE
–
RIE
TIE
SSR
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(–)
(–)
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
SIDR (read)
SODR (write)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0
Read/write
Initial value
Serial status register
Address: channel 0 000023
H
: channel 1 000027
H
: channel 2 000047
H
bit
Read/write
Initial value
–
–
–
–
DIV3 DIV1 DIV1 DIV0
CDCR
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(W)
(1)
(W)
(1)
(W)
(1)
(W)
(1)
15
14
13
12
11
10
9
8
Machine clock division
control register
Address: channel 0 000051
H
: channel 1 000053
H
: channel 2 000055
H
Input data register/
Output data register
Address: channel 0 000022
H
: channel 1 000026
H
: channel 2 000046
H