參數(shù)資料
型號: MB90587
廠商: Fujitsu Limited
英文描述: Octal Bus Transceivers With 3-State Outputs 20-CFP -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 40/124頁
文件大?。?/td> 2638K
代理商: MB90587
MB90580B Series
40
2.
Timebase Timer
The time-base timer consists of a 18-bit timer and an interval interrupt control circuit. Note that the time-base
timer uses the oscillation clock regardless of the setting of the MCS bit in the CKSCR.
(1) Register configuration
(2) Block Diagram
Timebase timer control register
bit
15
14
(
)
(
)
13
(
) (R/W) (R/W) (W) (R/W) (R/W)
(
)
(0)
(0)
12
11
10
TBR
9
8
Address : 0000A9
H
Reserved
(R/W)
(1)
TBIE TBOF
TBC1 TBC0
TBTC
Access
Initial value
(1)
(0)
(0)
TBTC
PONR
STBR
WRST
ERST
SRST
TBC0
TBR
TBIE
TBOF
TBC1
WT1
WT0
WTE
WTC
WDCS
SCE
WTC2
WTC1
WTC0
WTR
WTIE
WTOF
WDTC
WDTC
WT2
AND
CLR
OF
CLR
2
12
2
14
2
16
2
19
TBTRES
2
10
2
13
2
14
2
15
WTRES
2
11
2
13
2
15
2
18
2
10
2
13
2
14
2
15
Clock timer
Q
R
S
AND
Q
R
S
AND
Q
R
S
Time-base
interrupt
Clock
interrupt
Selector
Selector
Selector
Main clock
Clock input
Time-base timer
Watchdog reset
generator
2-bit
counter
Clock input
To WDGRST
internal reset
generator
From power-on reset
generator
From hardware standby
control circuit
Subclock
From RST bit in STBYC
register
From RST pin
F
2
M
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