參數(shù)資料
型號: MB90574CPMT
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP120
封裝: 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù): 18/135頁
文件大小: 2504K
代理商: MB90574CPMT
18
MB90570 Series
The series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs
should not become indeterminate. (MB90F574,MB90F574A,MB90574C)
12. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. Turn on the power again
to initialize these registers.
13. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may
fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal
state.
14. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions
The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corre-
sponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB,
ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the
instruction will not be placed in the instruction operand register.
15. Precautions for Use of REALOS
Extended intelligent I/O service (EI
2
OS) cannot be used, when REALOS is used.
Oscillation setting time *
2
V
CC
(power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operating clock A) signal
KB (internal operating clock B) signal
PORT (port output) signal
Step-down circuit setting time *
1
Period of indeterminate
*1: Step-down circuit setting time 2
17
/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)
*2: Oscillation setting time
2
18
/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)
Timing chart of indeterminate outputs from ports 0 and 1
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