參數(shù)資料
型號(hào)： MB90568PF
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-bit Proprietary Microcontrollers
中文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 20 MM, 3.35 MM HEIGHT, 1 MM PITCH, PLASTIC, QFP-64
文件頁(yè)數(shù)： 47/91頁(yè)
文件大?。?/td> 484K
代理商： MB90568PF
MB90560/565 Series
47
7.
DTP/External Interrupt Circuit
(1) Overview of the DTP/external interrupt circuit
The DTP (Data Transfer Peripheral) /external interrupt circuit detects interrupt requests input to the external
interrupt input pins (INT7 to INT0) and outputs interrupt requests.
DTP/external interrupt circuit functions
The DTP/external interrupt function detects edge or level signals input to the external interrupt input pins (INT7
to INT0) and outputs interrupt requests.
The interrupt request is received by the CPU and, if the extended intelligent I/O service (EI
2
OS) is enabled,
EI
2
OS performs automatic data transfer (DTP function) then passes control to the interrupt handler routine on
completion. If EI
2
OS is disabled, control passes directly to the interrupt handler routine without performing
automatic data transfer (DTP function) .
Overview of the DTP/external interrupt circuit
External Interrupt
DTP/external interrupt circuit interrupts and EI
2
OS
: Available when the interrupt shared with ICR07 or ICR08 is not used.
Channel
Interrupt
No.
Interrupt Control Register
Vector Table Address
EI
2
OS
Register Name
Address
Lower
Upper
Bank
INT0/INT1
#25 (19
H
)
ICR07
0000B7
H
FFFF98
H
FFFF99
H
FFFF9A
H
INT2/INT3
#26 (1A
H
)
FFFF94
H
FFFF95
H
FFFF96
H
INT4/INT5
#27 (1B
H
)
ICR08
0000B8
H
FFFF90
H
FFFF91
H
FFFF92
H
INT6/INT7
#28 (1C
H
)
FFFF8C
H
FFFF8D
H
FFFF8E
H
ICR : Interrupt control register
DTP Function
Input pins
8 channels (P10/INT0 to P16/INT6, P63/INT7)
Interrupt conditions
The level or edge to detect can be set independently for each pin in the detection lev-
el setup register (ELVR) .
“L” level, “H” level, rising edge, or falling edge input
Interrupt number
#25 (19
H
) to #28 (1C
H
)
Interrupt control
Interrupts can be enabled or disabled in the DTP/external interrupt enable register
(ENIR) .
Interrupt flag
The DTP/external interrupt request register (ENRR) stores interrupt requests.
Set EI
2
OS to disabled (ICR : ISE
=
0)
Processing selection
Set EI
2
OS to enabled (ICR : ISE
=
1)
Jumps to interrupt handler routine after
automatic data transfer by EI
2
OS com-
pletes.
Operation
Jumps to interrupt handler routine
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