參數(shù)資料
型號(hào): MB90565
廠商: Fujitsu Limited
英文描述: 16-bit Proprietary Microcontrollers
中文描述: 16位微控制器專有
文件頁數(shù): 50/91頁
文件大?。?/td> 484K
代理商: MB90565
MB90560/565 Series
50
9.
8/10-Bit A/D Converter
Overview of the 8/10-bit A/D converter
The 8/10-bit A/D converter uses RC successive approximation to convert analog input voltages to an 8-bit or
10-bit digital value.
The input signals can be selected from the eight analog input pin channels.
8/10-bit A/D converter functions
8/10-bit A/D converter conversion modes
Conversion Mode
8/10-bit A/D converter interrupts and EI
2
OS
Interrupt Control Register
: Available
A/D conversion time
The minimum conversion time is 6.13
μ
s (for a 16 MHz machine clock, including sampling
time) .
The minimum sampling time is 2.0
μ
s (for a 16 MHz machine clock)
Conversion method RC successive approximation with sample & hold circuit
Resolution
8-bit or 10-bit, selectable
Analog input pins
Eight analog input pin channels are available. The input pin can be selected by the program.
Interrupts
An interrupt request can be generated and EI
2
OS invoked when A/D conversion completes.
The conversion data protection function operates when A/D conversion is performed with
the interrupt enabled.
A/D conversion
start trigger
The conversion start trigger can be set from the following options : software, output of 16-
bit reload timer 1 (rising edge) , or zero detection edge from 16-bit freerun timer.
EI
2
OS support
Supported by the extended intelligent I/O service (EI
2
OS) .
Single Conversion Mode Operation
Scan Conversion Mode Operation
Single-shot conversion mode 1
Single-shot conversion mode 2
Performs one conversion for the spec-
ified channel (1 channel) then halts.
Sequentially performs one conversion
for multiple channels (up to 8 channels
can be set) , then halts.
Continuous conversion mode
Performs repeated conversions for the
specified channel (1 channel) .
Performs repeated conversions for the
specified channels (up to 8 channels
can be set) .
Incremental conversion mode
Performs one conversion for the spec-
ified channel (1 channel) then halts
and waits for the next activation.
Sequentially performs one conversion
for multiple channels (up to 8 channels
can be set) , then halts and waits for
the next activation.
Interrupt No.
Vector Table Address
EI
2
OS
Register Name
Address
Lower
Upper
Bank
#11 (0B
H
)
ICR00
0000B0
H
FFFFD0
H
FFFFD1
H
FFFFD2
H
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