- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377926 > MB90552B (Fujitsu Limited) Triple 3-Input Positive-AND Gates 20-LCCC -55 to 125 PDF資料下載
參數(shù)資料
| 型號(hào)： | MB90552B |
| 廠商： | Fujitsu Limited |
| 英文描述： | Triple 3-Input Positive-AND Gates 20-LCCC -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 44/58頁(yè) |
| 文件大?。?/td> | 695K |
| 代理商： | MB90552B |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)當(dāng)前第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)
MB90550A/550B Series
44
(13) I
2
C Interface
(V
CC
=
5.0 V
±
10%, V
SS
=
AV
SS
=
0.0 V, T
A
=
40
°
C to +85
°
C)
Value
Notes: “m” and“n” in the above table represent the values of shift clock frequency setting bits (CS4 to CS0) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
t
DOSUO
represents the minimum value when the interrupt period is equal to or greater than the SCL “L” width.
The SDA and SCL output values indicate that that rise time is 0 ns.
Parameter
Symbol
Pin name
Unit
Remarks
Min.
Max.
Internal clock cycle time
t
CP
—
62.5
666
ns
All products
Start condition output
t
STAO
SDA0 to SDA2
SCL0 toSCL2
t
CP
×
m
×
n/2 – 20 t
CP
×
m
×
n/2 + 20
t
CP
(m
×
n/2 + 4)
– 20
ns
Only as master
Stop condition output
t
STOO
t
CP
(m
×
n/2 + 4)
+ 20
ns
Start condition detection
t
STAI
3 t
CP
+ 40
—
ns
Only as slave
Stop condition detection
t
STOI
3 t
CP
+ 40
t
CP
×
m
×
n/2 – 20 t
CP
×
m
×
n/2 + 20
t
CP
(m
×
n/2 + 4)
– 20
—
ns
SCL output “L” width
t
LOWO
SCL0 to SCL2
ns
Only as master
SCL output “H” width
t
HIGHO
t
CP
(m
×
n/2 + 4)
+ 20
ns
SDA output delay time
Setup after SDA output
interrupt period
SCL input “L” width
t
DOO
SDA0 to SDA2
SCL0 to SCL2
2 t
CP
– 20
2 t
CP
+ 20
ns
t
DOSUO
4 t
CP
– 20
—
ns
t
LOWI
SCL0 to SCL2
3 t
CP
+ 40
—
ns
SCL input “H” width
t
HIGHI
t
CP
+ 40
—
ns
SDA input setup time
t
SUI
SDA0 to SDA2
SCL0 to SCL2
40
—
ns
SDA input hold time
t
HOI
0
—
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB90552BPF | Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125 |
| MB90552BPFV | Triple 3-Input Positive-AND Gates 14-CFP -55 to 125 |
| MB90553A | Triple 3-Input Positive-AND Gates 20-LCCC -55 to 125 |
| MB90553APF | Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125 |
| MB90553APFV | Triple 3-Input Positive-AND Gates 14-CFP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB90552BPF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90552BPFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90552BPMC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90553A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB90553APF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。