參數(shù)資料
型號(hào): MB90523PFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP120
封裝: PLASTIC, QFP-120
文件頁(yè)數(shù): 64/106頁(yè)
文件大小: 1539K
代理商: MB90523PFV
MB90520 Series
64
12. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks. By using this module,
hardware interrupt requests to the CPU can be generated and cancelled using software.
This module does not conform to the extended intelligent I/O service (EI
2
OS).
(1) Register Configuration
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this
register with “1” generates a delay interrupt request. Programming this register with “0” cancels a delay interrupt
request. Upon a reset, an interrupt is canceled. The undefined bit area can be programmed with either “0” or
“1.” For future extension, however, it is recommended that bit set and clear instructions be used to access this
register.
(2) Block Diagram
Delayed interrupt factor generation/cancellation register (DIRR)
bit 15
Address
00009F
H
R0
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
Initial value
XXXXXXX0
B
R/W: Readable and writable
— : Undefined bits (read value undefined)
Note: Upon a reset, an interrupt is cancelled.
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt number
S factor
R latch
R0
Internal data bus
Interrupt request signal
#42*
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