參數(shù)資料
型號(hào): MB90523
廠商: Fujitsu Limited
英文描述: Quadruple 2-Input Positive-NAND Gates 20-LCCC -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 44/106頁
文件大?。?/td> 1539K
代理商: MB90523
MB90520 Series
44
5. 16-bit Re-load Timer 0, 1 (With an Event Count Function)
The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal
clocks and an event count mode for counting down by detecting a given edge of the pulse input to the external
bus pin. Either of the two functions can be selectively used.
For this timer, an “underflow” is defined as the timing of transition from the counter value of “0000
H
” to “FFFF
H
.”
According to this definition, an underflow occurs after a counter value of [re-load register setting value + 1] .
In operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after
an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used.
Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent
I/O service (EI
2
OS).
The MB90520 series has 2 channels of 16-bit re-load timers.
(1) Register Configuration
MOD0 OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
Timer control status register lower digits ch.0, ch.1 (TMCSR0, TMCSR1 : L)
bit 7
bit 6
bit 5
TMCSR0 : 000048
H
TMCSR1 : 00004C
H
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000
B
Initial value
Timer control status register upper digits ch.0, ch.1 (TMCSR0, TMCSR1 : H)
bit 15
bit 14
bit 13
TMCSR0 : 000049
H
TMCSR1 : 00004D
H
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
R/W
R/W
R/W
XXXX0000
B
Initial value
CSL1
CSL0
MOD2 MOD1
16-bit timer register upper and lower digits ch.0, ch.1 (TMR0, TMR1)
Address
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 bit 0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Address
Address
TMR0 : 00004B
H
00004A
H
TMR1 : 00004E
H
00004F
H
16-bit re-load register upper and lower digits ch.0, ch.1 (TMRLR0, TMRLR1)
Address
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1 bit 0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
TMRLR0 : 00004B
H
00004A
H
TMRLR1 : 00004E
H
00004F
H
R/W : Readable and writable
R : Read only
W : Write only
X : Indeterminate
— : Undefined bits (read value undefined)
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