參數資料
型號: MB90487PFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-bit Proprietary Microcontroller CMOS
中文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數: 61/113頁
文件大?。?/td> 522K
代理商: MB90487PFV
MB90480/485 Series
61
14. Watchdog timer
The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as acount
clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated.
(1) Register List
(2) Block Diagram
Watchdog timer control register (WDTC)
0000A8
H
Read/write
Initial value
X
R
X
R
X
R
X
W
1
W
1
W
1
7
6
5
4
3
2
1
0
R
X
PONR
WRST
ERST
SRST
WTE
WT1
WT0
Reserved
PONR
WRST ERST SRST WTE
WT1
WT0
×
2
1
×
2
2
×
2
8
×
2
9
×
2
10
×
2
11
×
2
12
×
2
13
×
2
14
×
2
15
×
2
16
×
2
17
×
2
18
×
2
1
SCLK
CLR
CLR
×
2
2
×
2
8
×
2
9
×
2
10
×
2
11
×
2
12
×
2
13
×
2
14
×
2
15
×
2
16
×
2
17
×
2
18
2
4
4
Watchdog timer control register (WDTC)
Watchdog timer
Watch mode start
Timebase timer
mode start
Sleep mode start
Hold status start
Counter
clear circuit
Count
clock
selector
2-bit
counter
Watchdog
reset
generator
circuit
Clear
Internal
reset
generator
circuit
CLR and
start
Time-base counter
HCLK
×
2
HCLK : Oscillator clock
SCLK : Sub clock
Watch timer control
register (WTO)
WDCS bit
Clock select register
(CKSCR)
SCM bit
Stop mode
start
Re-
served
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