參數(shù)資料
型號(hào)： MB90487PF
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 108/113頁(yè)
文件大?。?/td> 1195K
代理商： MB90487PF
MB90480/485 Series
94
(8) Hold Timing
(VCC
= 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
* : tCP : See “ (1) Clock Timing Standards”.
Note : One or more cycles are required from the time the HRQ pin is read until the HAK signal changes.
(9) UART Timing
(VCC
= 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40 °C to +85 °C)
*1 : CL is the load capacitance applied to pins for testing.
*2 : tCP : See “ (1) Clock Timing Standards”.
Note : AC ratings are for CLK synchronized mode.
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
Pin floating
→HAK↓time
tXHAL
HAK
30
tCP*ns
HAK
↓→pin valid time
tHAHV
HAK
tCP
2 tCP*ns
Parameter
Symbol
Pin
Conditions
Value
Unit
Remarks
Min
Max
Serial clock cycle time
tSCYC
Internal shift clock
mode output pins :
CL*1
= 80 pF + 1 TTL
8 tCP*2
ns
SCK
↓→SOT delay time
tSLOV
80
+80
ns
120
+120
ns
fcp
= 8 MHz
Valid SIN
→SCK↑
tIVSH
100
ns
200
ns
fcp
= 8 MHz
SCK
↑→valid SIN hold time
tSHIX
tCP*2
ns
Serial clock “H” pulse width
tSHSL
External shift clock
mode output pins :
CL*1
= 80 pF + 1 TTL
4 tCP*2
ns
Serial clock “L” pulse width
tSLSH
4 tCP*2
ns
SCK
↓→SOT delay time
tSLOV
150
ns
200
ns
fcp
= 8 MHz
Valid SIN
→SCK↑
tIVSH
60
ns
120
ns
fcp
= 8 MHz
SCK
↑→valid SIN hold time
tSHIX
60
ns
120
ns
fcp
= 8 MHz
HAK
tXHAL
tHAHV
2.4 V
0.8 V
2.4 V
0.8 V
Pins
High-Z
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