參數(shù)資料
型號: MB90487BPMC
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 3/124頁
文件大小: 3283K
代理商: MB90487BPMC
MB90480B/485B Series
100
DS07-13722-11E
(8) Hold Timing
(VCC
= 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40 °C to + 85 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : One or more cycles are required from the time the HRQ pin is read until the HAK signal changes.
(9) UART Timing
(VCC
= 2.7 V to 3.6 V, VSS = 0.0 V, TA = 40 °C to + 85 °C)
*1 : CL is the load capacitance applied to pins for testing.
*2 : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Note : The above rating is in CLK synchronous mode.
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Pin floating
→ HAK ↓ time
tXHAL
HAK
30
tCP*ns
HAK
↓ → pin valid time
tHAHV
HAK
tCP*2 tCP*ns
Parameter
Symbol
Pin
name
Conditions
Value
Unit
Remarks
Min
Max
Serial clock cycle time
tSCYC
Internal shift clock
mode output pins :
CL*1
= 80 pF + 1 TTL
8 tCP*2
ns
SCK
↓ → SOT delay time
tSLOV
80
+ 80
ns
120 + 120
ns
fCP
= 8 MHz
Valid SIN
→ SCK↑
tIVSH
100
ns
200
ns
fCP
= 8 MHz
SCK
↑ → valid SIN hold time
tSHIX
tCP*2
ns
Serial clock “H” pulse width
tSHSL
External shift clock
mode output pins :
CL*1
= 80 pF + 1 TTL
4 tCP*2
ns
Serial clock “L” pulse width
tSLSH
4 tCP*2
ns
SCK
↓ → SOT delay time
tSLOV
150
ns
200
ns
fCP
= 8 MHz
Valid SIN
→ SCK↑
tIVSH
60
ns
120
ns
fCP
= 8 MHz
SCK
↑ → valid SIN hold time
tSHIX
60
ns
120
ns
fCP
= 8 MHz
HAK
tXHAL
tHAHV
2.4 V
0.8 V
2.4 V
0.8 V
Pins
Hi-Z
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