• 參數(shù)資料
    型號: MB90485
    廠商: Fujitsu Limited
    英文描述: 16-bit Proprietary Microcontroller
    中文描述: 16位微控制器專有
    文件頁數(shù): 41/120頁
    文件大?。?/td> 1241K
    代理商: MB90485
    MB90480/485 Series
    41
    4.
    8/10-bit A/D Converter
    The A/D converter converts analog input voltage to digital values, and provides the following features.
    Conversion time : minimum 3.68
    μ
    s per channel
    (92 machine cycles at 25 MHz machine clock, including sampling time)
    Sampling time : minimum 1.92
    μ
    s per channel
    (48 machine cycles at 25 MHz machine clock)
    RC sequential comparison conversion method, with sample & hold circuit.
    8-bit or 10-bit resolution
    Analog input selection of 8 channels
    Single conversion mode : Conversion from one selected channel.
    Scan conversion mode : Conversion from multiple consecutive channels, programmable selection of up to
    8 channels.
    Continuous conversion mode : Repeated conversion of specified channels.
    Stop conversion mode : Conversion from one channel followed by a pause until the next activation allows to
    synchronize with conversion start.
    At the end of A/D conversion, an A/D conversion completed interrupt request can be generated to the CPU.
    The interrupt can be used activate the
    μ
    DMAC in order to transfer the results of A/D conversion to memory
    for efficient continuous processing.
    The starting factor conversion may be selected from software, external trigger (falling edge) , or timer (rising
    edge) .
    (1) Register List
    ADCS2, ADCS1 (Control status register)
    ADCS1
    Address : 000046
    H
    ADCR2, ADCR1 (Data register)
    ADCR1
    Address : 000048
    H
    Initial value
    Bit attributes
    ADCS2
    Address : 000047
    H
    Initial value
    Bit attributes
    Initial value
    Bit attributes
    ADCR2
    Address : 000049
    H
    Initial value
    Bit attributes
    0
    R/W
    0
    R/W
    0
    R/W
    0
    R/W
    0
    R/W
    0
    R/W
    0
    R/W
    7
    6
    5
    4
    3
    2
    1
    0
    MD0
    0
    R/W
    MD1
    ANS2
    ANS1
    ANS0
    ANE2
    ANE1
    ANE0
    0
    R/W
    0
    R/W
    0
    R/W
    0
    R/W
    0
    R/W
    0
    W
    0
    R/W
    15
    14
    13
    12
    11
    10
    9
    8
    INT
    0
    R/W
    BUSY
    INTE
    PAUS
    STS1
    STS0
    STRT
    Reserved
    X
    R
    X
    R
    X
    R
    X
    R
    X
    R
    X
    R
    X
    R
    7
    6
    5
    4
    3
    2
    1
    0
    D6
    X
    R
    D7
    D5
    D4
    D3
    D2
    D1
    D0
    0
    W
    0
    W
    0
    W
    0
    W
    X
    R
    X
    R
    X
    R
    15
    14
    13
    12
    11
    10
    9
    8
    ST1
    0
    W
    S10
    ST0
    CT1
    CT0
    D9
    D8
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