參數(shù)資料
型號: MB90455
廠商: Fujitsu Limited
英文描述: Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-CDIP -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 27/78頁
文件大?。?/td> 680K
代理商: MB90455
MB90455 Series
27
Port 5 pins block diagram
Port 5 registers
Port 5 registers include port 5 data register (PDR5), port 5 direction register (DDR5), and analog input
permission register (ADER).
Analog input permission register (ADER) allows or disallows input of analog signal to the analog input pin.
The bits configuring the register correspond to port 5 pins on a one-to-one basis.
Relation between port 5 registers and pins
Port name
Bits of register and corresponding pins
Port 5
PDR5, DDR5
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADER
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Corresponding pins
P57
P56
P55
P54
P53
P52
P51
P50
ADER
Pch
Nch
Standby control: Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode
(SPL=1).
Port data register (PDR)
PDR read
Output latch
PDR write
Port direction register (DDR)
Direction
Pin
latch
DDR write
DDR read
Standby control (SPL=1)
I
Analog input
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