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參數(shù)資料
| 型號： | MB90427GPF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Original Microcontroller |
| 中文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 45/99頁 |
| 文件大?。?/td> | 1706K |
| 代理商： | MB90427GPF |
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MB90420G/5G (A) Series
45
8.
DTP/External Interrupt Circuit
The DTP (Data transfer peripheral) /external interrupt circuit is located between an externally connected periph-
eral device and the F
2
MC-16LX CPU and sends interrupt requests or data transfer requests generated from the
peripheral device to the CPU, thereby generating external interrupt requests or starting the expanded intelligent
I/O services (EI
2
OS) .
(1) DTP/external interrupt function
The DTP/external interrupt function uses a signal input from the DTP/external interrupt pin as a startup source.
And it is accepted by the CPU by the same procedure as a normal hardware interrupt, and can generate an
external interrupt or start the expanded intelligent I/O service (EI
2
OS) .
When the interrupt is accepted by the CPU, if the corresponding expanded intelligent I/O service (EI
2
OS) is
prohibited the interrupt operates as an external interrupt function and branches to an interrupt routine. If the
EI
2
OS is permitted the interrupt functions as a DTP function, using EI
2
OS for automatic data transfer, then
branching to an interrupt routine after the completion of the specified number of data transfers.
ICR : Interrupt control register
External interrupt
DTP function
Input pins
8 pins (P50/INT0 to P53/INT3, P00/INT4 to P03 INT7)
Interrupt sources
Request level setting register (ELVR) sets the detection level, or selected edge for
each pin
“H” level/ “L” level/ rising edge/falling
edge input
“H” level/ “L” level input
Interrupt numbers
#16 (10
H
) , #18 (12
H
) , #20 (14
H
) , #22 (16
H
) , #24 (18
H
) , #26 (1A
H
)
Interrupt control
DTP/interrupt enable register (ENIR) permits/prohibits interrupt request output
Interrupt flags
DTP/interrupt enable register (EIRR) stores interrupt sources
When EI
2
OS prohibited (ICR : ISE
=
0)
Process selection
When EI
2
OS is enabled (ICR : ISE
=
1)
EI
2
OS performs automatic data transfer,
then after a specified number of cycles,
branches to an interrupt routine
Processing
Branch to external interrupt processing
routine
相關PDF資料 |
PDF描述 |
|---|---|
| MB90427GPFV | 16-Bit Original Microcontroller |
| MB90428GPF | 16-Bit Original Microcontroller |
| MB90F428GPFV | 16-Bit Original Microcontroller |
| MB90428GPFV | 16-Bit Original Microcontroller |
| MB90F423G | Octal Transparent D-type Latches With 3-State Outputs 20-CDIP -55 to 125 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB90427GPFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-Bit Original Microcontroller |
| MB90428G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-Bit Original Microcontroller |
| MB90428GA | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-Bit Original Microcontroller |
| MB90428GAPF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-Bit Original Microcontroller |
| MB90428GAPFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16-Bit Original Microcontroller |
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