參數(shù)資料
型號: MB90352CSPFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64
封裝: PLASTIC, LQFP-64
文件頁數(shù): 34/64頁
文件大?。?/td> 800K
代理商: MB90352CSPFV
MB90350 Series
4
s PRODUCT LINEUP
(Continued)
Part Number
Parameter
MB90F352/S/C/CS, MB90352/S/C/CS*1
MB90V340/S
CPU
F2MC-16LX CPU
System clock
On-chip PLL clock multiplier (
×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL
× 6)
ROM
Boot-block, Flash memory
128 Kbytes
External
RAM
4 Kbytes
30 Kbytes
Emulator-specific
power supply*2
Yes
Technology
0.35
m CMOS with on-chip voltage regulator for internal
power supply
+ Flash memory with
On-chip charge pump for programming voltage
0.35
m CMOS with
on-chip voltage regulator
for internal power supply
Operating
voltage range
3.5 V - 5.5 V : at normal operating (not using A/D converter)
4.0 V - 5.5 V : at using A/D converter/Flash programming
4.5 V - 5.5 V : at using external bus
5 V
± 10%
Temperature range
40 °C to +105 °C (125 °C up to 16 MHz machine clock)
Package
LQFP-64
PGA-299
UART
2 channels
3 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbit/s)
devices with ‘C’-suffix
: 1 channel
devices without ‘C’-suffix :
1 channel
A/D
Converter
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3
s include sample time (per one channel)
16-bit Reload Timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys
= Machine clock frequency)
Supports External Event Count function
16-bit
I/O Timer
(2 channels)
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys
= Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare
(4 channels)
Signals an interrupt when 16-bit I/O Timer match output compare registers.
A pair of compare registers can be used to generate an output signal.
16-bit Input Capture
(6 channels)
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
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