參數(shù)資料
型號: MB90348CPFV
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 61/76頁
文件大小: 1041K
代理商: MB90348CPFV
MB90340 Series
64
(8) UART0/1/2/3/4
(TA
= 40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)
* : Refer to “ (1) Clock timing” rating for tCP (internal operating clock cycle time).
Notes :
AC characteristic in CLK synchronized mode.
CL is load capacity value of pins when testing.
tCP is the machine cycle (Unit : ns)
Parameter
Symbol
Pin
Condition
Value
Unit Remarks
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK4
Internal clock
operation output
pins are
CL
= 80 pF + 1 TTL.
8 tCP*
ns
SCK
↓ → SOT delay time
tSLOV
SCK0 to SCK4,
SOT0 to SOT4
80
+80
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to SCK4,
SIN0 to SIN4
100
ns
SCK
↑ → Valid SIN hold time
tSHIX
SCK0 to SCK4,
SIN0 to SIN4
60
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK4
External clock
operation output
pins are
CL
= 80 pF + 1 TTL.
4 tCP*
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK4
4 tCP*
ns
SCK
↓ → SOT delay time
tSLOV
SCK0 to SCK4,
SOT0 to SOT4
150
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to SCK4,
SIN0 to SIN4
60
ns
SCK
↑ → Valid SIN hold time
tSHIX
SCK0 to SCK4,
SIN0 to SIN4
60
ns
Internal Shift Clock Mode
SCK
2.4 V
tSCYC
0.8 V
SOT
0.8 V
2.4 V
0.8 V
tSLOV
SIN
VIL
VIH
tIVSH
VIL
VIH
tSHIX
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