參數(shù)資料
型號: MB90333APMC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP120
封裝: 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-120
文件頁數(shù): 89/120頁
文件大?。?/td> 1210K
代理商: MB90333APMC
MB90330A Series
70
12. 8/10-bit A/D converter
The A/D converter converts analog input voltages into digital values and has the following features.
RC sequential compare conversion method with sample and hold circuit
Selectable 8-bit resolution or 10-bit resolution
Analog input program-selectable from among 16 channels
Single conversion mode : Convert 1 selected channel
Scan conversion mode : Continuous plural channels (maximum 16 channels can be programmed) are converted.
Continuous conversion mode : Repeatedly convert the specified channels.
Stop conversion mode: Convert 1 channel then suspend conversion to remain on standby until the next
activation (Simultaneous conversion start available).
An interrupt request to the CPU can be generated upon completion of A/D conversion. Suitable for continuous
processing as this interrupt activates
DMA to transfer the data resulting from A/D conversion to memory.
The activation source can be selected from among software, external trigger (falling edge), and timer (rising
edge).
Register list
A/D control status register lower/upper (ADCS0/ADCS1)
A/D data register lower/upper (ADCR0/ADCR1)
A/D conversion channel selection register (ADMR)
bit
Initial Value
Address : 000040H
00 - - - - - 0B
bit
Initial Value
Address : 000041H
00000000B
bit
Initial Value
Address : 000042H
XXXXXXXXB
bit
Initial Value
Address : 000043H
00101XXXB
bit
Initial Value
Address : 000045H
00000000B
( R/W )
(
)( )( )( )( )
( R/W )
76
5
4
3
2
1
0
MD0
( R/W )
MD1
Reserved
( R/W )
( W )
( R/W )
15
14
13
12
11
10
9
8
INT
( R/W )
BUSY
INTE
PAUS
STS1
STS0
STRT
Reserved
( R )
76
5
4
3
2
1
0
D6
( R )
D7
D5
D4
D3
D2
D1
D0
( W )
(
)
( R )
15
14
13
12
11
10
9
8
ST1
( R/W )
S10
ST0
CT1
CT0
D9
D8
( R/W )
15
14
13
12
11
10
9
8
ANS2
( R/W )
ANS3
ANS1
ANS0
ANE3
ANE2
ANE1
ANE0
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