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參數(shù)資料
| 型號： | MB89W665C-SH |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 10 MHz, MICROCONTROLLER, CDIP64 |
| 封裝： | WINDOWED, SHRINK, CERAMIC, DIP-64 |
| 文件頁數(shù)： | 28/47頁 |
| 文件大?。?/td> | 649K |
| 代理商： | MB89W665C-SH |
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34
MB89660R Series
7. A/D Converter
Input impedance of analog input pins
The A/D converter used for the MB89660R series contains a sample hold circuit as illustrated below to fetch
analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 2 k
).
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx.
0.1
F for the analog input pin.
Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
VOT
VNT
V( N+I )T
VFST
Digital output
(1 LSB
× N + VOT)
0000
0001
0010
1111
1110
1111
1 LSB =
AVR
256
Linearity error =
VNT – (1 LSB
× N + VOT)
1 LSB
Differential linearity error =
V( N + 1 ) T – VNT
1 LSB
Analog input
Actual conversion value
Theoretical conversion value
– 1
Total error =
1 LSB
VNT – (1 LSB
× N + 1 LSB)
Linearity error
Closes for 8 instruction cycles
after starting A/D conversion.
Sample hold circuit
C
33 pF
Analog channel selector
Analog input pin
R
6 k
Comparator
If the output impedance of
the external circuit is high, it
is recommended to connect
an external capacitor of
approx. 0.1
F.
.
.=
.
.=
Analog Input Equivalent Circuit
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